Phase mixer and delay locked loop including the same

ABSTRACT

A phase mixer includes a first driver configured to drive a first input signal to a mixing node with a driving force determined by a first setting value, a second driver configured to drive a second input signal to the mixing node with a driving force determined by a second setting value, and a slew rate control unit configured to control a slew rate at the mixing node.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No. 10-2011-0107599, filed on Oct. 20, 2011, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field

Exemplary embodiments of the present invention relate to a phase mixer and a delay locked loop.

2. Description of the Related Art

A phase mixer is a circuit which mixes two signals with different phases and generates a mixed signal with an intermediate phase between the phases of the two signals. The phase of the mixed signal generated by the phase mixer is changed depending upon at which ratio the two signals are mixed. For example, if a first signal and a second signal are mixed at the ratio of M:N, as M/N increases, the phase of a mixed signal approaches the phase of the first signal, and as M/N decreases, the phase of a mixed signal approaches the phase of the second signal. Since the phase mixer can finely control the phase of a mixed signal between the phases of two signals, the phase mixer is used in a delay locked loop (DLL), etc.

FIG. 1 is a configuration diagram of a conventional phase mixer.

Referring to FIG. 1, the phase mixer includes a first driver 110, a second driver 120, and an buffer 130.

Hereinafter, operations of the phase mixer will be described with reference to FIG. 1.

The first driver 110 drives a first clock FCLK to a mixing node MN with a driving force that is determined in response to a code CD<0:3>. For this operation, the first driver 110 includes a plurality of inverters 111 to 114 which are activated or deactivated by the respective bits CD<0> to CD<3> of the code CD<0:3>.

The second driver 120 drives a second clock SCLK to the mixing node MN with a driving force that is determined in response to an inverted code CDB<0:3>, which is obtained by inverting the code CD<0:3>. According to an example, the second driver 120 includes a plurality of inverters 121 to 124, which are activated or deactivated by the respective bits CDB<0> to CDB<3> of the inverted code CDB<0:3>. For illustration purposes, the respective bits CD<0> to CD<3> of the code CD<0:3> and the respective bits CDB<0> to CDB<3> of the inverted code CDB<0:3> are in inverted relationships.

The buffer 130 buffers the signal of the mixing node MN and outputs the buffered signal to an output node OUT. For this operation, the buffer 130 may be an inverter which outputs a high level to the output node OUT when the voltage level of the mixing node MN is lower than a reference level (a logic threshold, that is, a reference voltage for discriminating a high level and a low level) and outputs a low level to the output node OUT when the voltage level of the mixing node MN is higher than the reference level.

The first driver 110 drives the first clock FCLK output to the mixing node MN more strongly as the number of bits with a high value of ‘1’ increases among the respective bits of the code CD<0:3>, and the second driver 120 drives the second clock SCLK output to the mixing node MN more strongly as the number of bits with a high value of ‘1’ increases among the respective bits of the inverted code CDB<0:3>. For example, if the value of the code CD<0:3> is ‘0001’ (the value of the inverted code CDB<0:3> is ‘1110’), a ratio between the driving force for driving the first clock FCLK to the mixing node MN and the driving force for driving the second clock SCLK to the mixing node MN becomes 1:3. If the value of the code CD<0:3> is ‘0111’ (the value of the inverted code CDB<0:3> is ‘1000’), a ratio between the driving force for driving the first clock FCLK to the mixing node MN and the driving force for driving the second clock SCLK to the mixing node MN becomes 3:1. If the value of the code CD<0:3> is ‘1111’ (the value of the inverted code CDB<0:3> is ‘0000’), for example, only the first clock FCLK is driven to the mixing node MN, and if the value of the code CD<0:3> is ‘0000’ (the value of the inverted code CDB<0:3> is ‘1111’), for example, only the second clock SCLK is driven to the mixing node MN. The phase of the signal (hereinafter, referred to as an output signal OUT) outputted to the output node OUT is changed according to the driving forces for driving the first clock FCLK and the second clock SCLK to the mixing node MN.

The phase mixer may be used as a fine delay line for finely controlling the phase of a clock in a delay locked loop (DLL). As to details of using a phase mixer as a fine delay line of a delay locked loop, such details are disclosed in Korean Patent Application No. 10-2009-0133426 (entitled “a delay locked loop circuit”), which is incorporated herein by reference in its entirety.

When a phase mixer is used in a delay locked loop, in order to suppress the occurrence of a jitter, a phase change amount in the output signal of the phase mixer is constant with respect to a change in the code CD<0:3>. That is to say, in the cases where the code CD<0:3> changes from ‘0000’ to ‘0001’, from ‘0001’ to ‘0011’, from ‘0011’ to ‘0111’ and from ‘0111’ to ‘1111’, the phase change amounts in the output signals of the phase mixer are the same with one another (namely, each time the value of the code CD<0:3> is changed by a unit value (for example, 1 bit), the phase of the output signal of the phase mixer is changed by a period equal to the unit value when the phase difference between the first clock FCLK and the second clock SCLK is divided into four equal periods).

In general, when the phase difference between the first clock FCLK and the second clock SCLK is small, the phase mixer operates as described above. However, as the phase difference between the first clock FCLK and the second clock SCLK increases, the phase mixer deviates from the above-described operations.

FIG. 2 is a waveform diagram illustrating a feature in the conventional phase mixer as the phase difference between the first clock FCLK and a second clock SCLK increases.

For illustration purposes, the waveforms of the first clock FCLK and the second clock SCLK are independently shown in FIG. 2 assuming that the code CD<0:3> is changed from ‘0000’ sequentially to ‘0001’, ‘0011’ and ‘0111’ (the inverted code CDB<0:3> is changed from ‘1111’ sequentially to ‘1110’, ‘1100’ and ‘1000’). The waveform of the signal (hereinafter, referred to as a “mixed signal MN”) generated at the mixing node MN corresponds to a waveform in which the waveform of the first clock FCLK and the waveform of the second clock SCLK are summed with each other (at each time, the sum of the value of the first clock FCLK and the value of the second clock SCLK becomes the value of the mixed signal MN).

Depending upon whether the level of the mixed signal MN is higher or lower than a reference level 201 (the mixed signal MN has a high level or a low level), a high level or a low level is outputted to the output node OUT. Therefore, times A1 to A4 at which the reference level 201 and the mixed signal MN cross each other correspond to times at which the logic value of the output signal OUT is changed. Thus, by observing how the times A1 to A4 at which the reference level 201 and the mixed signal MN cross with each other are moved as the value of the code CD<0:3> is changed, a change in the phase of the output signal OUT is changed as the value of the code CD<0:3> is determined.

Referring to FIG. 2, it can be seen that, when the phase difference between the first clock FCLK and the second clock SCLK is large, the phase change amounts 202, 203 and 204 of the output signal OUT are not constant as the code CD<0:3> is changed from ‘0000’ sequentially to ‘0001’, ‘0011’ and ‘0111’ (the phase change amounts 202, 203 and 204 gradually increase). In other words, when the phase difference between the first clock FCLK and the second clock SCLK is large, the phase change amounts of the output signal OUT are not constant even though the code CD<0:3> is sequentially changed by the unit value (for example, 1 bit). Due to such features, a jitter is likely to increase in the delay locked loop.

SUMMARY

An embodiment of the present invention is directed to a phase mixer which can mix phases at a precise ratio according to the value of a code for controlling a mixing ratio even when two signals with a large phase difference are mixed.

In accordance with an embodiment of the present invention, a phase mixer includes: a first driver configured to drive a first input signal to a mixing node with a driving force determined by a first setting value; a second driver configured to drive a second input signal to the mixing node with a driving force determined by a second setting value; and a slew rate control unit configured to control a slew rate at the mixing node.

In accordance with another embodiment of the present invention, a delay locked loop includes: a first delay unit configured to delay an input clock and generate a first clock; a second delay unit configured to delay the input clock and generate a second clock; a first driver configured to drive the first clock to a mixing node with a driving force determined by a first setting value; a second driver configured to drive the second clock to the mixing node with a driving force determined by a second setting value; a slew rate control unit configured to control a slew rate at the mixing node; an buffer configured to buffer a signal of the mixing node and output the buffered signal to an output node; a replica delay unit configured to delay a clock outputted to the output node and generate a feedback clock; a phase comparison unit configured to compare phases of the input clock and the feedback clock; and a control unit configured to control delay values of the first delay unit and the second delay unit in response to a comparison result of the phase comparison unit and generate the first setting value and the second setting value.

In accordance with yet another embodiment of the present invention, a phase mixer includes: a phase mixing unit configured to mix a first input signal and a second input signal at a ratio determined by setting values and output a signal obtained from the mixing to a mixing node; and a slew rate control unit configured to control a slew rate at the mixing node.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a configuration diagram of a conventional phase mixer.

FIG. 2 is a waveform diagram illustrating a feature in the conventional phase mixer as a phase difference between a first clock and a second clock increases.

FIG. 3 is a configuration diagram of a phase mixer in accordance with an embodiment of the present invention.

FIG. 4 is a waveform diagram illustrating the operations of the phase mixer in accordance with the embodiment of the present invention when a phase difference between a first input signal and a second input signal is larger than a reference value.

FIG. 5 is a configuration diagram of a delay locked loop in accordance with another embodiment of the present invention.

FIG. 6 is a configuration diagram of a phase mixer in accordance with another embodiment of the present invention.

DETAILED DESCRIPTION

Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

In the following descriptions, a ‘high’ level, a logic ‘high’ value, ‘high’, a logic value ‘1’, and ‘1’ each represent a logic high value, and a ‘low’ level, a logic ‘low’ value, ‘low’, a logic value ‘0’, and ‘0’ each represent a logic low value. The level of each signal when activated may be a ‘high’ level or a ‘low’ level (the level of the signal when deactivated is opposite to the level of the signal when activated) and may be changed for different signals and different design needs.

FIG. 3 is a configuration diagram of a phase mixer in accordance with an embodiment of the present invention.

Referring to FIG. 3, a phase mixer may include a first driver 310 configured to drive a first input signal FCLK to a mixing node MN with a driving force that is determined by a first setting value SET1<0:3>, a second driver 320 configured to drive a second input signal SCLK to the mixing node MN with a driving force that is determined by a second setting value SET2<0:3>, a slew rate control unit 330 configured to control a slew rate at the mixing node MN, and an buffer 340 configured to buffer the signal of the mixing node MN and output the buffered signal to an output node OUT.

The first input signal FCLK, the second input signal SCLK and the signal (hereinafter, referred to as an “output signal OUT”) outputted to the output node OUT may be clock signals. The slew rate means a maximum variation rate of an output voltage per unit time and is expressed by V/μs (voltage per microsecond). If the slew rate is large, a speed at which the output voltage varies becomes fast, and if the slew rate is small, the speed at which the output voltage varies becomes slow. The first setting value SET1<0:3> and the second setting value SET2<0:3> may be binary codes of a single bit or multiple bits. Hereinbelow, binary signals of 4 bits will be used for illustration purposes.

Hereinafter, operations of the phase mixer will be described with reference to FIG. 3.

The first driver 310 drives the first input signal FCLK to the mixing node MN with the driving force that is determined in response to the first setting value SET1<0:3>. According to an example, the first driver 310 may include a plurality of first unit drivers 311 to 314 which are activated or deactivated in response to the respective bits SET1<0> to SET1<3> of the first setting value SET1<0:3>. Among the plurality of first unit drivers 311 to 314, one or more first unit driver may be activated and drive the first input signal FCLK to the mixing node MN, and one or more first unit driver may be deactivated from driving the first input signal FCLK to the mixing node MN. Accordingly, depending upon the number of first unit drivers which are activated among the plurality of first unit drivers 311 to 314, a driving force by which the first input signal FCLK is driven to the mixing node MN is determined. While the first unit drivers may be inverters for inverting inputs and driving the inverted inputs as outputs as can be seen from FIG. 3, the present invention is not limited to such. The first unit drivers may be circuits for buffering inputs and driving the buffered inputs as outputs or circuits for transmitting inputs as outputs. The first driver 310 is not necessarily limited to the configuration shown in FIG. 3, and any circuits may be used as the first driver 310 so long as they can perform an operation of driving the first input signal FCLK to the mixing node MN with the driving force that is determined according to the first setting value SET1<0:3>.

The second driver 320 drives the second input signal SCLK to the mixing node MN with the driving force that is determined in response to the second setting value SET2<0:3> (that is, SET2<0:3> and SET2B<0:3>). For this operation, the second driver 320 may include a plurality of second unit drivers 321 to 324 which are activated or deactivated in response to the respective bits SET2<0> to SET2<3> of the second setting value SET2<0:3>. Among the plurality of second unit drivers 321 to 324, one or more second unit drivers may be activated and drive the second input signal SCLK to the mixing node MN, and one or more second unit drivers may be deactivated from driving the second input signal SCLK to the mixing node MN. Accordingly, depending upon the number of second unit drivers which are activated among the plurality of second unit drivers 321 to 324, a driving force by which the second input signal SCLK is driven to the mixing node MN is determined. While the second unit drivers may be inverters for inverting inputs and driving the inverted inputs as outputs as can be seen from FIG. 3, the present invention is not necessarily limited to such. The second unit drivers may be circuits for buffering inputs and driving the buffered inputs as outputs or circuits for transmitting inputs as outputs. The second driver 320 is not necessarily limited to the configuration shown in FIG. 3, and any circuits may be used as the second driver 320 so long as they can perform an operation of driving the second input signal SCLK to the mixing node MN with the driving force that is determined according to the second setting value SET2<0:3>.

Here, the sum of the first setting value SET1<0:3> and the second setting value SET2<0:3> may be constantly maintained. In particular, in the case where the sum of the first setting value SET1<0:3> and the second setting value SET2<0:3> is constantly maintained as ‘1111’, the first setting value SET1<0:3> and the second setting value SET2<0:3> are in a relationship in which their logic values are inverted with respect to each other. For example, if the first setting value SET1<0:3> is ‘0011’, the second setting value SET2<0:3> becomes ‘1100’ which is obtained by inverting ‘0011’, and if the first setting value SET1<0:3> is ‘0111’, the second setting value SET2<0:3> becomes ‘1000’ which is obtained by inverting ‘0111’. For reference, SET1B<0:3> is a signal which is obtained by inverting the first setting value SET1<0:3>, and SET2B<0:3> is a signal which is obtained by inverting the second setting value SET2<0:3>.

The ratio, at which the first input signal FCLK and the second input signal SCLK are driven to the mixing node MN according to the first setting value SET1<0:3> and the second setting value SET2<0:3>, is determined in response to the value of the code CD<0:3> and the value of the inverted code CDB<0:3> as described above with reference to FIG. 1. The first setting value SET1<0:3> corresponds to the code CD<0:3>, and the second setting value SET2<0:3> corresponds to the inverted code CDB<0:3>.

The slew rate control unit 330 controls a slew rate at the mixing node MN. The slew rate control unit 330 decreases the slew rate at the mixing node MN if a phase difference between the first input signal FCLK and the second input signal SCLK is larger than a reference value. That is to say, if a phase difference between the first input signal FCLK and the second input signal SCLK is larger than the reference value, the slew rate control unit 330 causes the voltage of the mixing node MN to vary slow (the slope of a waveform decreases in the graph showing a change in the voltage of the mixing node MN with respect to a time). Hereinafter, the reference numeral 330A represents a first example of the slew rate control unit 330, and the reference numeral 3308 represents a second example of the slew rate control unit 330.

For the above-described operation, in the first exemplary embodiment 330A, the slew rate control unit 330 may include a transistor 331A having one end connected to the mixing node MN and the other end connected to an internal node NO and turned on or off in response to a control signal SL which is activated when the phase difference between the first input signal FCLK and the second input signal SCLK is larger than the reference value, and a capacitor 332A having one end which is connected to the internal node NO and the other end to which a ground voltage VSS is applied. The positions of the transistor 331A and the capacitor 332A may be changed with each other. Namely, the capacitor 332A may be connected between the mixing node MN and the internal node NO, and the transistor 331A may have one end connected to the internal node NO and the other end to which the ground voltage VSS is applied.

The capacitor 332A performs a function of stabilizing the voltage of the node connected thereto from fluctuating. Therefore, if the control signal SL is activated (has a high level), the transistor 331A is turned on, and the one end of the capacitor 332A is electrically connected to the mixing node MN. Due to this fact, a speed at which the voltage of the mixing node MN is changed becomes slow (a slew rate decreases). Conversely, if the control signal SL is deactivated (has a low level), the transistor 332A is turned off, and the mixing node MN and the one end of the capacitor 332A are electrically disconnected from each other. Due to this fact, a speed at which the voltage of the mixing node MN is changed becomes fast (a slew rate increases).

Otherwise, in the second exemplary embodiment 330B, the slew rate control unit 330 may include a transistor 331B having one end which is connected to the mixing node MN and turned on or off in response to the control signal SL which is activated when the phase difference between the first input signal FCLK and the second input signal SCLK is larger than the reference value, and a resistive element 332B having one end connected to the mixing node MN and the other end connected to the other end of the transistor 3318.

Since the resistive element 332B limits current flow, it performs a function of preventing the voltage of the node connected thereto from being changed. Therefore, if the control signal SL is activated (has a high level), the transistor 331B is turned off, and current flows through the resistive element 332B between the mixing node MN and the input end of the buffer 340. Due to this fact, a speed at which the voltage of the mixing node MN is changed becomes slow (a slew rate decreases). Conversely, if the control signal SL is deactivated (has a low level), the transistor 331B is turned on, and the mixing node MN and the input end of the buffer 340 are electrically connected with each other via the transistor 331B. Accordingly, current does not flow through the resistive element 332B but through the transistor 331B between the mixing node MN and the input end of the buffer 340. Therefore, since current flow is not limited by the resistive element 332B, a speed at which the voltage of the mixing node MN is changed becomes fast (a slew rate increases).

While it is illustrated in FIG. 3 that the slew rate control unit 330 includes any one of the capacitor 332A and the resistive element 332B, the slew rate control unit 330 may include both the capacitor 332A and the resistive element 332B. A degree at which a slew rate is changed at the mixing node MN may be controlled by controlling the capacitance value of the capacitor 332A and the resistance value of the resistive element 332B.

The reason why the slew rate control unit 330 is activated when the phase difference between the first input signal FCLK and the second input signal SCLK is larger than the reference value and is deactivated when the phase difference is smaller than the reference value is as follows. As aforementioned with reference to FIG. 2, the feature where a phase change amount of the output signal OUT according to a change in the code CD<0:3> is not constant is likely to occur as the phase difference between the first input signal FCLK and the second input signal SCLK becomes large. In this regard, if the slew rate at the mixing node MN is decreased so as to address such a feature, since signal transmission is correspondingly delayed, the high speed operation of the phase mixer is limited (that is, if the slew rate is low, the phase mixer does not appropriately operate when a high frequency signal is inputted). Therefore, since reducing a jitter and improving performance at a high frequency are at an inverse proportional relationship to one another, the reference value is preset such that the slew rate can be decreased by activating the slew rate control unit 330 when the phase difference between the first input signal FCLK and the second input signal SCLK is larger than the reference value and can be increased by deactivating the slew rate control unit 330 when the phase difference between the first input signal FCLK and the second input signal SCLK is smaller than the reference value. More specifically, according an example, only when the phase difference between the input signals is large, the slew rate is decreased at the mixing node MN to reduce a jitter, and when the phase difference between the input signals is small, the slew rate is increased at the mixing node MN to ensure the high speed operation of the phase mixer.

The buffer 340 buffers the signal of the mixing node MN and outputs the buffered signal to the output node OUT. According to an example, the buffer 340 may include an inverter which outputs a high level to the output node OUT when the voltage level of the mixing node MN is smaller than a reference level (a logic threshold) (when the mixing node MN has a low level) and outputs a low level to the output node OUT when the voltage level of the mixing node MN is larger than the reference level (when the mixing node MN has a high level). However, exemplary embodiments of the present invention are not limited to such an example. It is sufficient that the buffer 340 includes a circuit which outputs an output signal with a high level or a low level depending upon whether an input signal is lower or higher than a reference level (as in an inverter, the circuit may output the output signal with a logic value opposite to the logic value of the input signal or may output the output signal with the same logic value as the logic value of the input signal). The slew rate control unit 330 is directly linked to the buffer 340 through the mixing node MN.

Describing the entire operations of the phase mixer, the first driver 310 drives the first input signal FCLK to the mixing node MN with the driving force that is determined by the first setting value SET1<0:3>. The second driver 320 drives the second input signal SCLK to the mixing node MN with the driving force that is determined by the second setting value SET2<0:3>. At this time, according to the driving forces of the first driver 310 and the second driver 320, the waveform of the voltage of the mixing node MN is changed, and due to this fact, the phase of the output signal OUT is changed. The phase of the output signal OUT has a value between the phase of the first input signal FCLK and the phase of the second input signal SCLK, and the precise value thereof varies depending upon the first setting value SET1<0:3> and the second setting value SET2<0:3>. The slew rate control unit 330 is activated when the phase difference between the first input signal FCLK and the second input signal SCLK is larger than the reference value and decreases the slew rate of the voltage of the mixing node MN to ensure that a phase change amount of the output signal OUT according to changes in the first setting value SET1<0:3> and the second setting value SET2<0:3> is constant.

In the phase mixer in accordance with the embodiment of the present invention, when the phase difference between the first input signal FCLK and the second input signal SCLK is larger than the reference value, the slew rate of the voltage of the mixing node MN is decreased to ensure that a phase change amount of the output signal OUT according to changes in the first setting value SET1<0:3> and the second setting value SET2<0:3> is constant. Also, when the phase difference between the first input signal FCLK and the second input signal SCLK is larger than the reference value, the slew rate of the voltage of the mixing node MN is not decreased to ensure the high frequency operation of the phase mixer.

FIG. 4 is a waveform diagram illustrating the operations of the phase mixer in accordance with the embodiment of the present invention when a phase difference between the first input signal FCLK and the second input signal SCLK is larger than the reference value.

For illustration purposes, the waveforms of the first clock FCLK and the second clock SCLK are independently shown in FIG. 4. The waveform of the signal (hereinafter, referred to as a “mixed signal MN”) generated in the mixing node MN corresponds to a waveform in which the waveform of the first input signal FCLK and the waveform of the second input signal SCLK are summed with each other (at each time, the sum of the value of the first input signal FCLK and the value of the second input signal SCLK becomes the value of the mixed signal MN).

Here, waveforms corresponding to the first setting value SET1<0:3> are sequentially shown as the first setting value SET1<0:3> is changed in the same manner as the code CD<0:3> in FIG. 2 (the second setting value SET2<0:3> is changed in the same manner as the inverted code CDB<0:3> in FIG. 2). The first setting value SET1<0:3> has the same value as the code CD<0:3> of FIG. 2, and the second setting value SET2<0:3> has the same value as the inverted code CDB<0:3>.

Depending upon whether the level of the mixed signal MN is higher or lower than a reference level 401 (the level of the mixed signal MN is high or low), a high level or a low level is outputted to the output node OUT. Therefore, times A1 to A4 at which the reference level 401 and the mixed signal MN cross each other correspond to times at which the logic value of the output signal OUT is changed. Thus, by observing how the times A1 to A4 at which the reference level 401 and the mixed signal MN cross each other are moved as the value of the first setting value SET1<0:3> is changed, the phase change amount of the output signal OUT is determined as the value of the first setting value SET1<0:3> is changed.

As can be seen from FIG. 4, in the phase mixer in accordance with the embodiment of the present invention shown in FIG. 3, unlike the conventional phase mixer, even though the phase difference between the first input signal FCLK and the second input signal SCLK is large, phase change amounts 402, 403 and 404 of the output signal OUT according to changes in the first setting value SET1<0:3> and the second setting value SET2<0:3> are constant.

FIG. 5 is a configuration diagram of a delay locked loop in accordance with another embodiment of the present invention. The delay locked loop shown in FIG. 5 includes the phase mixer shown in FIG. 3.

Referring to FIG. 5, the delay locked loop includes a first delay unit 510 configured to delay an input clock ICLK and generate a first clock FCLK, a second delay unit 520 configured to delay the input clock ICLK and generate a second clock SCLK, a phase mixing unit 530 configured to mix the phases of the first clock FCLK and the second clock SCLK in response to a first setting value SET1<0:3> and a second setting value SET2<0:3> and generate an output clock OCLK, a replica delay unit 540 configured to delay the output clock OCLK and generate a feedback clock FBCLK, and a phase comparison unit 550 configured to compare the phases of the input clock ICLK with the feedback clock FBCLK, and a control unit 560 configured to control the delay values of the first delay unit 510 and the second delay unit 520 in response to a comparison result of the phase comparison unit 550 and generate the first setting value SET1<0:3> and the second setting value SET2<0:3>.

Hereinafter, operations of the delay locked loop will be described with reference to FIG. 5.

The first delay unit 510 and the second delay unit 520 delay the input clock ICLK and respectively output the first clock FCLK and the second clock SCLK. The delay values of the first delay unit 510 and the second delay unit 520 are changed by a first unit delay value or a second unit delay value at a time according to a comparison result of the phase comparison unit 550.

According to an example, the first delay unit 510 includes a plurality of first unit delay units 511 which have the first unit delay value as the delay value and are activated or deactivated by the control unit 560, and a plurality of second unit delay units 512 which have the second unit delay value larger than the first unit delay value as the delay value and are activated or deactivated by the control unit 560. Also, the second delay unit 520 includes a plurality of third unit delay units 521 which have the first unit delay value as the delay value and are activated or deactivated by the control unit 560, and a plurality of fourth unit delay units 522 which have the second unit delay value as the delay value and are activated or deactivated by the control unit 560. The delay value of the first delay unit 510 and the delay value of the second delay unit 520 may have a difference corresponding to the first unit delay value or the second unit delay value. According to an example, the first delay unit 510 and the second delay unit 520 correspond to a coarse delay line of a delay locked loop which relatively coarsely controls the delay value of the output clock OCLK.

The configuration and operation of the phase mixing unit 530 are the same as the phase mixer shown in FIG. 3. More specifically, the phase mixing unit 530 includes a first driver 310, a second driver 320, a slew rate control unit 330, and an buffer 340. The first clock FCLK corresponds to the first input signal FCLK, the second clock SCLK corresponds to the second input signal SCLK, and the output clock OCLK corresponds to the output signal OUT (the signal outputted to the output node OUT). For illustration purposes, it is assumed that the first unit delay value is smaller than the reference value described above in detail with reference to FIG. 3 and the second unit delay value is larger than the reference value. Thus, if the difference between the delay value of the first delay unit 510 and the delay value of the second delay unit 520 corresponds to the first unit delay value, the slew rate control unit 330 is deactivated, and if the difference between the delay value of the first delay unit 510 and the delay value of the second delay unit 520 corresponds to the second unit delay value, the slew rate control unit 330 is activated. According to an example, the phase mixing unit 530 corresponds to a fine delay line of a delay locked loop which finely controls the phase of the output clock OCLK.

The replica delay unit 540 outputs the feedback clock FBCLK by delaying the output clock OCLK by a delay value acquired through modeling a clock delay component inside a semiconductor device (for example, a semiconductor memory device) in which a delay locked loop is included, and the phase comparison unit 550 outputs a result of comparing the input clock ICLK and the feedback clock FBCLK.

The control unit 560 controls the delay values of the first delay unit 510 and the second delay unit 520 according to the comparison result of the phase comparison unit 550, and generates the first setting value SET1<0:3> and the second setting value SET2<0:3>. Namely, the control unit 560 controls the delay value of the output clock OCLK according to the comparison result of the phase comparison unit 550. In the case where the phase of the input clock ICLK is earlier than the phase of the feedback clock FBCLK, the control unit 560 decreases the delay value of the output clock OCLK, and in an opposite case, the control unit 560 increases the delay value of the output clock OCLK. Moreover, in order to control the slew rate control unit 330, when the difference between the delay value of the first delay unit 510 and the delay value of the second delay unit 520 corresponds to the first unit delay value, the control unit 560 deactivates the control signal SL (deactivates the slew rate control unit 330), and when the difference between the delay value of the first delay unit 510 and the delay value of the second delay unit 520 corresponds to the second unit delay value, the control unit 560 activates the control signal SL (activates the slew rate control unit 330).

According to an example, if the delay value of the first delay unit 510 and the delay value of the second delay unit 520 are changed by the first unit delay value at a time, the difference between the delay value of the first delay unit 510 and the delay value of the second delay unit 520 corresponds to the first unit delay value, and if the delay value of the first delay unit 510 and the delay value of the second delay unit 520 are changed by the second unit delay value at a time, the difference between the delay value of the first delay unit 510 and the delay value of the second delay unit 520 corresponds to the second unit delay value. Accordingly, the control unit 560 may deactivate the control signal SL when the delay value of the first delay unit 510 and the delay value of the second delay unit 520 are changed by the first unit delay value at a time and may activate the control signal SL when the delay value of the first delay unit 510 and the delay value of the second delay unit 520 are changed by the second unit delay value at a time.

Hereinbelow, operations of the delay locked loop will be described mainly with respect to the operation of the phase mixing unit 530.

First, if a delay locking operation is started, the first delay unit 510 and the second delay unit 520 delay the input clock ICLK by a minimum delay value and generate the first clock FCLK and the second clock SCLK. The phase mixing unit 530 mixes the phases of the first clock FCLK and the second clock SCLK according to the initial setting values (the initial values of SET1<0:3> and SET2<0:3>) and generates the output clock OCLK. The replica delay unit 540 delays the output clock OCLK and generates the feedback clock FBCLK, and the phase comparison unit 550 compares the phases of the input clock ICLK and the feedback clock FBCLK. According to a phase comparison result of the phase comparison unit 550, the phase of the output clock OCLK is changed by the first unit delay value or the second unit delay value (the phase of the output clock OCLK is controlled by the first delay unit 510 and the second delay unit 520: hereinafter, referred to as a ‘coarse control step’). Subsequently, according to a phase comparison result of the phase comparison unit 550, if the phase difference between the input clock ICLK and the feedback clock FBCLK becomes smaller than the first unit delay value or the second unit delay value, the phase of the output clock OCLK is finely controlled by the phase mixing unit 530 (hereinafter, referred to as a ‘fine control step’).

In the case where the phase difference between the first clock FCLK and the second clock SCLK corresponds to the first unit delay value, since the first unit delay value is smaller than the reference value, the slew rate control unit 330 of the phase mixing unit 530 is in the deactivated state (the control signal SL is deactivated). In the case where the phase difference between the first clock FCLK and the second clock SCLK corresponds to the second unit delay value, since the second unit delay value is larger than the reference value, the slew rate control unit 330 of the phase mixing unit 530 is in the activated state (the control signal SL is activated). Accordingly, in the delay locked loop according to the exemplary embodiment of the present invention, even when the phase difference between the first clock FCLK and the second clock SCLK becomes the second unit delay value (that is, becomes larger than the reference value), the phase change amount of the output clock OCLK according to a change in the setting values SET1<0:3> and SET2<0:3> is constantly maintained (the phase is changed by ¼ times the second unit delay value each time the setting values SET1<0:3> and SET2<0:3> are changed by one bit).

Even in the case of a delay locked loop which uses the conventional phase mixer, if the phase difference between the first clock FCLK and the second clock SCLK corresponds to the first unit delay value (that is, is smaller than the reference value), the phase change amount of the output clock OCLK according to a change in the setting values SET1<0:3> and SET2<0:3> is constant to ¼ times the first delay value. However, as aforementioned in detail with reference to FIGS. 1 and 2, if the phase difference between the first clock FCLK and the second clock SCLK corresponds to the second unit delay value (larger than the reference value), the phase change amount of the output clock OCLK according to a change in the setting values SET1<0:3> and SET2<0:3> is not constant at ¼ times the second delay value.

In the delay locked loop using the phase mixer in accordance with the embodiment of the present invention, even when the phase difference between the first clock FCLK and the second clock SCLK is larger than the second unit delay value (larger than the reference value), the phase change amount of the output clock OCLK according to a change in the setting values SET1<0:3> and SET2<0:3> is constantly maintained at ¼ times the second unit delay value by controlling the slew rate of the mixing node MN using the slew rate control unit 330 included in the phase mixing unit 530, whereby a jitter is reduced.

Here, the reason why the first delay unit 510 and the second delay unit 520 include the second and fourth unit delay units 512 and 522 with the second unit delay value as the delay value is that, if unit delay units with a large delay value are used, the number of unit delay units necessary for obtaining the same delay value is decreased compared to when unit delay units with a small delay value are used, and thus, the number of registers for controlling unit delay units is decreased to thus reduce the area of a delay locked loop.

FIG. 6 is a configuration diagram of a phase mixer in accordance with another embodiment of the present invention.

Referring to FIG. 6, the phase mixer includes a phase mixing unit 610 configured to mix the phases of a first input signal FCLK and a second input signal SCLK at a ratio determined by setting values SET1<0:3> and SET2<0:3> and outputting a resultant signal to a mixing node MN, a slew rate control unit 620 configured to control a slew rate at the mixing node MN, and an buffer 630 configured to buffer the signal of the mixing node MN and output the buffered signal to the an output node OUT. The phase mixing unit 610 mixes the phases of the first input signal FCLK and the second input signal SCLK at the ratio determined in response to the setting values SET1<0:3> and SET2<0:3> and outputs the resultant signal to the mixing node MN. According to an example, the phase mixing unit 610 may include the first driver 310 and the second driver 320 shown in FIG. 3. In other words, the phase mixing unit 610 may drive the first input signal FCLK and the second input signal SCLK to the mixing node MN at the ratio determined in response to the setting values SET1<0:3> and SET2<0:3> and thereby may output the signal obtained by mixing the phases of the first input signal FCLK and the second input signal SCLK at the ratio determined according to the setting values SET1<0:3> and SET2<0:3> at the mixing node MN. Detailed operations of the phase mixing unit 610 are the same as described with reference to FIG. 3. However, the configuration of the phase mixing unit 610 is not necessarily limited to the configuration including the first driver 310 and the second driver 320 shown in FIG. 3, and all circuits may be used as the phase mixing unit 610 so long as they can perform an operation of mixing the phases of the first input signal FCLK and the second input signal SCLK at the ratio determined according to the setting values SET1<0:3> and SET2<0:3>.

The configuration and operations of the slew rate control unit 620 are the same as those of the slew rate control unit 330 shown in FIG. 3. According to an example, the slew rate control unit 620 includes a transistor 621 to be turned on or off by receiving a control signal SL and a capacitor 622. Here, the slew rate control unit 620 may include a transistor or a resistive element or both of a transistor and a resistive element as described above in detail with reference to FIG. 3. Furthermore, the first exemplary embodiment 330A of the slew rate control unit 330 shown in FIG. 3 and the slew rate control unit 620 shown in FIG. 6 are circuits for performing substantially the same function while a sequence in which the transistor and the capacitor are connected is different.

The configuration and operations of the buffer 630 are the same as those of the buffer 340 shown in FIG. 3.

The phase mixer shown in FIG. 6 operates in the same manner and has the same effects as the phase mixer shown in FIG. 3.

As is apparent from the above descriptions, in the phase mixer in accordance with the embodiments of the present invention, a signal is obtained by mixing two signals at a precise ratio according to the value of a code for controlling a mixing ratio (for example, by decreasing a slew rate at a node to which the two signals are driven when a phase difference between the two signals to be mixed is large).

While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims. 

What is claimed is:
 1. A phase mixer comprising: a first driver configured to drive a first input signal to a mixing node with a driving force determined by a first setting value; a second driver configured to drive a second input signal to the mixing node with a driving force determined by a second setting value; and a slew rate control unit configured to control a slew rate at the mixing node.
 2. The phase mixer of claim 1, wherein the slew rate control unit is configured to be activated when a phase difference between the first input signal and the second input signal is larger than a reference value.
 3. The phase mixer of claim 2, wherein the slew rate control unit comprises: a transistor having one end connected to the mixing node and the other end connected to an internal node and turned on/off in response to a control signal, wherein the control signal is activated when the phase difference between the first input signal and the second input signal is larger than the reference value; and a capacitor having one end connected to the internal node and the other end connected to receive a ground voltage.
 4. The phase mixer of claim 2, wherein the slew rate control unit comprises: a transistor having one end connected to the mixing node and turned on/off in response to a control signal, wherein the control signal is activated when the phase difference between the first input signal and the second input signal is larger than the reference value; and a resistive element having one end connected to the mixing node and the other end connected to the other end of the transistor.
 5. The phase mixer of claim 1, wherein a sum of the first setting value and the second setting value is maintained at a constant value.
 6. The phase mixer of claim 1, further comprising: an buffer configured to buffer a signal of the mixing node and output the buffered signal to an output node.
 7. The phase mixer of claim 1, wherein the first driver comprises a plurality of first unit drivers configured to be activated or deactivated in response to respective bits of the first setting value, and wherein the second driver comprises a plurality of second unit drivers configured to be activated or deactivated in response to respective bits of the second setting value.
 8. The phase mixer of claim 6, wherein the first input signal, the second input signal and the signal outputted to the output node comprise clock signals.
 9. A delay locked loop comprising: a first delay unit configured to delay an input clock and generate a first clock; a second delay unit configured to delay the input clock and generate a second clock; a first driver configured to drive the first clock to a mixing node with a driving force determined by a first setting value; a second driver configured to drive the second clock to the mixing node with a driving force determined by a second setting value; a slew rate control unit configured to control a slew rate at the mixing node; an buffer configured to buffer a signal of the mixing node and output the buffered signal to an output node; a replica delay unit configured to delay a clock outputted to the output node and generate a feedback clock; a phase comparison unit configured to compare phases of the input clock and the feedback clock; and a control unit configured to control delay values of the first delay unit and the second delay unit in response to a comparison result of the phase comparison unit and generate the first setting value and the second setting value.
 10. The delay locked loop of claim 9, wherein the control unit is configured to activate the slew rate control unit when a phase difference between the first clock and the second clock is larger than a reference value.
 11. The delay locked loop of claim 10, wherein the slew rate control unit comprises: a transistor having one end connected to the mixing node and the other end connected to an internal node and turned on/off in response to a control signal, wherein the control signal is activated when the phase difference between the first clock and the second clock is larger than the reference value; and a capacitor having one end connected to the internal node and the other end connected to receive a ground voltage.
 12. The delay locked loop of claim 10, wherein the slew rate control unit comprises: a transistor having one end connected to the mixing node and the other end connected to an input of the buffer and turned on/off in response to a control signal, wherein the control signal is activated when the phase difference between the first clock and the second clock is larger than the reference value; and a resistive element having one end connected to the mixing node and the other end connected to the other end of the transistor.
 13. The delay locked loop of claim 9, wherein a sum of the first setting value and the second setting value is maintained at a constant value.
 14. The delay locked loop of claim 10, wherein the first delay unit comprises: a plurality of first unit delay units each having a delay of a first unit delay value; and a plurality of second unit delay units having a delay of a second unit delay value larger than the first unit delay value, and wherein the second unit delay unit comprises: a plurality of third unit delay units having a delay of the first unit delay value; and a plurality of fourth unit delay units having a delay of the second unit delay value.
 15. The delay locked loop of claim 14, wherein the phase difference between the first clock and the second clock corresponds to the first unit delay value or the second unit delay value and the first unit delay value is smaller than the reference value and the second unit delay value is larger than the reference value.
 16. The delay locked loop of claim 9, wherein the first driver comprises a plurality of first unit drivers configured to be activated or deactivated in response to respective bits of the first setting value, and wherein the second driver comprises a plurality of second unit drivers configured to be activated or deactivated in response to respective bits of the second setting value.
 17. A phase mixer comprising: a phase mixing unit configured to mix a first input signal and a second input signal at a ratio determined by setting values and output a signal obtained from the mixing to a mixing node; and a slew rate control unit configured to control a slew rate at the mixing node.
 18. The phase mixer of claim 17, wherein the slew rate control unit is configured to be activated when a phase difference between the first input signal and the second input signal is larger than a reference value.
 19. The phase mixer of claim 18, wherein the slew rate control unit comprises: a transistor having one end connected to the mixing node and the other end connected to an internal node and turned on/off in response to a control signal, wherein the control signal is activated when the phase difference between the first input signal and the second input signal is larger than the reference value; and a capacitor having one end connected to the internal node and the other end connected to receive a ground voltage.
 20. The phase mixer of claim 18, wherein the slew rate control unit comprises: a transistor having one end connected to the mixing node and turned on/off in response to a control signal, wherein the control signal is activated when the phase difference between the first input signal and the second input signal is larger than the reference value; and a resistive element having one end connected to the mixing node and the other end connected to the other end of the transistor. 